Cheng-gang Wang, Jian-hai Li, Jing Sun, Yan-li Sun
{"title":"基于功能建模的FPGA电路板测试诊断系统设计","authors":"Cheng-gang Wang, Jian-hai Li, Jing Sun, Yan-li Sun","doi":"10.1109/EMEIT.2011.6023800","DOIUrl":null,"url":null,"abstract":"Circuit boards composed of the boundary scan and non-boundary scan devices exist widely, and the fault detection and isolation of these non-boundary scan circuit boards is a puzzle for board-level maintenance and testing. Test methods based on boundary scan and digital I/O can not fulfill functional testing of entire circuit board. An automatic test system is constructed and a functional modeling method is put forward for FPGA circuit board testing. First, VITAL model is generated in FPGA development environment, achieving its functional modeling; then VITAL format configuration files and data are imported into LASAR, realizing circuit board simulation and fault simulation, and generating postprocessing documents; finally, postprocessing documents are input into ATE, and the automated testing and fault diagnosis of FPGA circuit board is implemented.","PeriodicalId":221663,"journal":{"name":"International Conference on Electronic and Mechanical Engineering and Information Technology","volume":"120 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of test and diagnosis system for FPGA circuit board based on functional modeling\",\"authors\":\"Cheng-gang Wang, Jian-hai Li, Jing Sun, Yan-li Sun\",\"doi\":\"10.1109/EMEIT.2011.6023800\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Circuit boards composed of the boundary scan and non-boundary scan devices exist widely, and the fault detection and isolation of these non-boundary scan circuit boards is a puzzle for board-level maintenance and testing. Test methods based on boundary scan and digital I/O can not fulfill functional testing of entire circuit board. An automatic test system is constructed and a functional modeling method is put forward for FPGA circuit board testing. First, VITAL model is generated in FPGA development environment, achieving its functional modeling; then VITAL format configuration files and data are imported into LASAR, realizing circuit board simulation and fault simulation, and generating postprocessing documents; finally, postprocessing documents are input into ATE, and the automated testing and fault diagnosis of FPGA circuit board is implemented.\",\"PeriodicalId\":221663,\"journal\":{\"name\":\"International Conference on Electronic and Mechanical Engineering and Information Technology\",\"volume\":\"120 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Electronic and Mechanical Engineering and Information Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EMEIT.2011.6023800\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Electronic and Mechanical Engineering and Information Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EMEIT.2011.6023800","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of test and diagnosis system for FPGA circuit board based on functional modeling
Circuit boards composed of the boundary scan and non-boundary scan devices exist widely, and the fault detection and isolation of these non-boundary scan circuit boards is a puzzle for board-level maintenance and testing. Test methods based on boundary scan and digital I/O can not fulfill functional testing of entire circuit board. An automatic test system is constructed and a functional modeling method is put forward for FPGA circuit board testing. First, VITAL model is generated in FPGA development environment, achieving its functional modeling; then VITAL format configuration files and data are imported into LASAR, realizing circuit board simulation and fault simulation, and generating postprocessing documents; finally, postprocessing documents are input into ATE, and the automated testing and fault diagnosis of FPGA circuit board is implemented.