谜语:在高层次设计描述上生成测试的基础

[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers Pub Date : 1988-06-27 DOI:10.1109/FTCS.1988.5300

Gabriel M. Silberman, I. Spillinger

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引用次数: 3

摘要

提出了一种形式化的方法来分析超大规模集成电路设计的高层描述，它产生有利于加速测试生成算法的信息。这种分析产生的信息可以用来减少回溯期间花费的工作量，通过引导决策(分配)过程来减少可能导致冲突的可能性，并最小化回溯之间的工作量。介绍了一种在信号数量上呈线性的时间内执行这种分析的算法RIDDLE。并给出了组合门级设计的特殊情况下的实验结果。

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RIDDLE: a foundation for test generation on a high level design description

A formal approach is presented to the analysis of a VLSI design described at the high level, which produces information conducive to the acceleration of test-generation algorithms. This analysis yields information which can be used to reduce the amount of effort expended during backtracking, by guiding this process towards decisions (assignments) less likely to cause conflicts and minimizing the amount of work between backtracks. RIDDLE, an algorithm that performs this analysis in time that is linear in the number of signals, is introduced. Experimental results for the special case of combinatorial gate-level designs are also given.<>

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[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers

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