{"title":"基于高级合成的VVC分数插值的FPGA实现","authors":"Ilker Hamzaoglu, Hossein Mahdavi, Elif Taskin","doi":"10.1109/ICCE53296.2022.9730363","DOIUrl":null,"url":null,"abstract":"In this paper, the first FPGA implementations of Versatile Video Coding (VVC) fractional interpolation algorithm using a high-level synthesis (HLS) tool in the literature are proposed. Three different C++ codes are developed. They implement constant multiplications with multiplication operations, addition and shift operations, and multiplierless constant multiplication algorithm, respectively. These C++ codes are synthesized using Xilinx Vivado HLS tool. The best proposed HLS implementation can process 62 full HD (1920×1080) video frames per second. It has higher performance than manual VVC fractional interpolation hardware implementations at the cost of larger area.","PeriodicalId":350644,"journal":{"name":"2022 IEEE International Conference on Consumer Electronics (ICCE)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"FPGA Implementations of VVC Fractional Interpolation Using High-Level Synthesis\",\"authors\":\"Ilker Hamzaoglu, Hossein Mahdavi, Elif Taskin\",\"doi\":\"10.1109/ICCE53296.2022.9730363\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the first FPGA implementations of Versatile Video Coding (VVC) fractional interpolation algorithm using a high-level synthesis (HLS) tool in the literature are proposed. Three different C++ codes are developed. They implement constant multiplications with multiplication operations, addition and shift operations, and multiplierless constant multiplication algorithm, respectively. These C++ codes are synthesized using Xilinx Vivado HLS tool. The best proposed HLS implementation can process 62 full HD (1920×1080) video frames per second. It has higher performance than manual VVC fractional interpolation hardware implementations at the cost of larger area.\",\"PeriodicalId\":350644,\"journal\":{\"name\":\"2022 IEEE International Conference on Consumer Electronics (ICCE)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-01-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Conference on Consumer Electronics (ICCE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCE53296.2022.9730363\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Consumer Electronics (ICCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE53296.2022.9730363","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA Implementations of VVC Fractional Interpolation Using High-Level Synthesis
In this paper, the first FPGA implementations of Versatile Video Coding (VVC) fractional interpolation algorithm using a high-level synthesis (HLS) tool in the literature are proposed. Three different C++ codes are developed. They implement constant multiplications with multiplication operations, addition and shift operations, and multiplierless constant multiplication algorithm, respectively. These C++ codes are synthesized using Xilinx Vivado HLS tool. The best proposed HLS implementation can process 62 full HD (1920×1080) video frames per second. It has higher performance than manual VVC fractional interpolation hardware implementations at the cost of larger area.
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