Methodology for improved event-driven system-level simulation of an RF transceiver subsystem for wireless SoCs

Digital assisted analog and RF concepts used in multi-standard multi-band wireless SoCs require a strong interaction between the analog and digital subsystems. Therefore functional verification of modern complex SoCs has evolved into a very challenging part in todays design flows. As an approach for an expedient verification process, an event-driven method based on SystemVerilog HDL is presented to perform time-efficient verification simulations of an entire RF transceiver frontend. To take into account signal properties, system behavior and certain error scenarios, methods like RF signal representation in the equivalent baseband, electrical signal modeling and true event-driven filter modeling are applied. A comparison to conventional simulation methodologies is given.