Time-multiplexed on-chip delay measurement for dependable high-speed digital LSIs

High-speed digital LSIs such as CPU, graphic processing LSI, and System-on-a-chip, are indispensable for all the today's consumer electrics. However, such today's high performance LSIs require careful debugging for timing related errors and high quality delay fault testing for the dependability. This paper presents time-multiplexed on-chip delay measurement to realize fast and high quality timing error debugging and delay fault testing. According to the experimental result, the measurement time of the proposed method is 2.5 % of the conventional one.