{"title":"提高SMT芯片中主线程性能的两种方法","authors":"Ma Pengyong, Chen Shuming, Hu Xiao","doi":"10.1109/NPC.2007.45","DOIUrl":null,"url":null,"abstract":"In SMT processor, every thread's executing time will be enlarged due to sharing resource by several threads. It will result in task lost in real time system. In this paper, we present two methods to alleviate the cache conflict in multithread chip, one is protecting the last instructions of master thread, and the other is locking loop. Both methods only need several additional registers. Simulations show that not only the performance of master thread is improved by 14%, but also the IPC of all threads is improved about 6%.","PeriodicalId":278518,"journal":{"name":"2007 IFIP International Conference on Network and Parallel Computing Workshops (NPC 2007)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Two methods to enhance the master thread's performance in SMT Chip\",\"authors\":\"Ma Pengyong, Chen Shuming, Hu Xiao\",\"doi\":\"10.1109/NPC.2007.45\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In SMT processor, every thread's executing time will be enlarged due to sharing resource by several threads. It will result in task lost in real time system. In this paper, we present two methods to alleviate the cache conflict in multithread chip, one is protecting the last instructions of master thread, and the other is locking loop. Both methods only need several additional registers. Simulations show that not only the performance of master thread is improved by 14%, but also the IPC of all threads is improved about 6%.\",\"PeriodicalId\":278518,\"journal\":{\"name\":\"2007 IFIP International Conference on Network and Parallel Computing Workshops (NPC 2007)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IFIP International Conference on Network and Parallel Computing Workshops (NPC 2007)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NPC.2007.45\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IFIP International Conference on Network and Parallel Computing Workshops (NPC 2007)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NPC.2007.45","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Two methods to enhance the master thread's performance in SMT Chip
In SMT processor, every thread's executing time will be enlarged due to sharing resource by several threads. It will result in task lost in real time system. In this paper, we present two methods to alleviate the cache conflict in multithread chip, one is protecting the last instructions of master thread, and the other is locking loop. Both methods only need several additional registers. Simulations show that not only the performance of master thread is improved by 14%, but also the IPC of all threads is improved about 6%.