Design of Arithmetic unit for RNS using 2n-3 as Base

Modular arithmetic is extensively used in cryptography and other applications. Choice of the base number for modular arithmetic is a critical factor. Folding of resulting numbers after a modulo operation is complex and needs special attention. In this paper, modulo 2n-3 architecture based on mapping of partial product bits under modulo operations is described. Each word of the partial product is mapped once normally and then with a bit left shift corresponding to the base number. In specific, an implementation of squarer is discussed with reference to bit folding in 2n-3 architecture. The results are compared with similar architectures described in available literature with respect to area and delay. The proposed architecture shows improvements in both area and delay.