FPGA Implementation of DC Bias Removal Filters – A Case Study with an ECG Signal

The study and processing of bio-signals and the perception of clinical images is an important part of modern medical science, technology and engineering. In each registered electrocardiogram (ECG) data, there are two major noise sources such as the power-line interface and baseline wandering noise. A low-frequency noise of about 0.5 to 0.6 Hz is the second, i.e. the baseline wander (closer to a dc). This wandering baseline is practically due to inadequate skin sensitivity to electrodes, i.e. due to relaxed interaction with electrodes or poor positioning or even tightly positioned electrodes. To suppress the DC offset, the conventional DC bias removal filter and its three variants are used in this study. All the circuits were synthesized on an Altera Cyclone IV FPGA EP4CE115F29C7 device using Quartus II software v13.1 tool. Finally, the simulation results of device utilization, clock speed, and power dissipation are compared among all the designs.