Failure Mechanism of Metallization Layer of a Multichip Module Substrate

The work described in this paper concentrates primarily on the multichip module type D. In MCM-D technologies, the interlayer vias have been identified as potential failure sites due to fatigue caused by temperature cycling and the CTE mismatch between the dielectric and metal layers. The selected model for this study uses an MCM-D structure, implementing aluminum-silicon (Al-Si) metallization layers separated by a silicon dioxide (SiO2) interlayer dielectric. A 3-D finite element analysis has performed on the model to determine the effect of accelerated temperature cycling and thermal shock. The resulting non-linear, elasto-plastic stress-strain response was obtained, under the von-Mises yield criterion, using PATRAN code. The fatigue life of the via was then estimated and compared with the experimental results.