Connectivity verification of zynq UltraScale+ MPSoC with TTC and WDT interrupts

Connectivity verification is very important to validate every design and the primary objective of the verification of a design is to check the correctness and performance of the Register-transfer level design against the specification. The aim of the project is to check the connectivity correctness and performance between the modules of the design. Project includes to write checks in System Verilog language to check connectivity of processor subsystem in zynq Ultrascale+ MpSoC contains low power and full power domain. A System Verilog based verification environment is developed. Here Verification is categorized into the following: “Whole system bring up” which includes booting of each processor and able to do some basic transfers to local memory i.e. Clock settings and some basic operations at system level. “Connectivity checks” which include the basic transaction to all modules at system level and toggle all ports. “Basic Functional Verification” which includes, Data Flow, Data Integrity through the system, address decoding etc., of each module at system level. Here Verification is for the Watchdog Timer (WDT) and Triple Timer Counter (TTC) blocks using advanced extensible interface (AXI) bus and advanced peripheral bus (APB) which generates different interrupts helps to avoid system malfunctions.