Parallel bit manipulation processor for communication coding and decoding

VLSI (Very Large-Scale Integration) designs for communication coding and decoding should, in general, provide high throughput, achieve low computing latency, occupy low silicon cost, and handle multiple bit manipulation algorithms. Application-Specific Instruction-set Processor (ASIP) is an optimized solution to fulfill all these requirements. This paper presents an ASIP for Cyclic Redundancy Check, Reed-Solomon, and basic bit manipulation operations. The processor is obtained via hardware/software co-design methodology and adopts single instruction multiple data architecture. The proposed design occupies 0.71mm2 (190 kgates) in 65nm CMOS process including 34.5KB single port memory and 45 kgates logic. The throughput of the proposed design reaches 128Gb/s, 8Gb/s, and 128Gb/s for basic bit manipulation operations, RS (255,239) decoding, and CRC calculation, respectively under the clock frequency of 1.0GHz. The proposed design is evaluated with state-of-the-art VLSI designs, which reveals its high performance, low silicon cost, and full programmability.