{"title":"硅兼容光互连和单片三维集成","authors":"K. Saraswat","doi":"10.1109/iedm13553.2020.9372100","DOIUrl":null,"url":null,"abstract":"While dimension scaling, introduction of new materials and novel device structures has enhanced the transistor performance, the opposite is true for the interconnects. Looking into the future the relentless scaling paradigm is threatened by the limits of copper/low-k interconnects. Thus, it is imperative to examine alternate interconnect schemes and explore possible advantages of novel potential candidates. Optical interconnects and three-dimensional (3-D) heterogeneous integration have emerged as potential candidates to mitigate the interconnect tyranny by providing lower power dissipation, improved communication bandwidth, and signal latency. This talk will focus on the most important devices and technologies for integration of these on the silicon platform.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Silicon compatible optical interconnect and monolithic 3-D integration\",\"authors\":\"K. Saraswat\",\"doi\":\"10.1109/iedm13553.2020.9372100\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"While dimension scaling, introduction of new materials and novel device structures has enhanced the transistor performance, the opposite is true for the interconnects. Looking into the future the relentless scaling paradigm is threatened by the limits of copper/low-k interconnects. Thus, it is imperative to examine alternate interconnect schemes and explore possible advantages of novel potential candidates. Optical interconnects and three-dimensional (3-D) heterogeneous integration have emerged as potential candidates to mitigate the interconnect tyranny by providing lower power dissipation, improved communication bandwidth, and signal latency. This talk will focus on the most important devices and technologies for integration of these on the silicon platform.\",\"PeriodicalId\":415186,\"journal\":{\"name\":\"2020 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/iedm13553.2020.9372100\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/iedm13553.2020.9372100","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Silicon compatible optical interconnect and monolithic 3-D integration
While dimension scaling, introduction of new materials and novel device structures has enhanced the transistor performance, the opposite is true for the interconnects. Looking into the future the relentless scaling paradigm is threatened by the limits of copper/low-k interconnects. Thus, it is imperative to examine alternate interconnect schemes and explore possible advantages of novel potential candidates. Optical interconnects and three-dimensional (3-D) heterogeneous integration have emerged as potential candidates to mitigate the interconnect tyranny by providing lower power dissipation, improved communication bandwidth, and signal latency. This talk will focus on the most important devices and technologies for integration of these on the silicon platform.