{"title":"高阶FIR滤波器的高性能对称混合形式设计","authors":"Jinghao Ye, M. Yanagisawa, Youhua Shi","doi":"10.1109/APCCAS50809.2020.9301685","DOIUrl":null,"url":null,"abstract":"In this paper, a symmetric hybrid form for high performance finite impulse response (FIR) filters with symmetric coefficients is proposed, which can be utilized in both fixed and reconfigurable FIR implementations to solve the driving capacity problem caused by the high fanout signals in the existing symmetric transposed form based FIR architecture. The evaluation results show that, when compared with the existing high speed FIR designs such as the symmetric systolic form in [13] and the hybrid form in [1], the proposed form can achieve significant area and power savings with great ADP and PDP reduction. Moreover, when compared with the symmetric systolic form in [13] the required latency can be approximately reduced by 33.3%, which clearly shows the performance improvement of the proposed method.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filters\",\"authors\":\"Jinghao Ye, M. Yanagisawa, Youhua Shi\",\"doi\":\"10.1109/APCCAS50809.2020.9301685\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a symmetric hybrid form for high performance finite impulse response (FIR) filters with symmetric coefficients is proposed, which can be utilized in both fixed and reconfigurable FIR implementations to solve the driving capacity problem caused by the high fanout signals in the existing symmetric transposed form based FIR architecture. The evaluation results show that, when compared with the existing high speed FIR designs such as the symmetric systolic form in [13] and the hybrid form in [1], the proposed form can achieve significant area and power savings with great ADP and PDP reduction. Moreover, when compared with the symmetric systolic form in [13] the required latency can be approximately reduced by 33.3%, which clearly shows the performance improvement of the proposed method.\",\"PeriodicalId\":127075,\"journal\":{\"name\":\"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS50809.2020.9301685\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS50809.2020.9301685","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filters
In this paper, a symmetric hybrid form for high performance finite impulse response (FIR) filters with symmetric coefficients is proposed, which can be utilized in both fixed and reconfigurable FIR implementations to solve the driving capacity problem caused by the high fanout signals in the existing symmetric transposed form based FIR architecture. The evaluation results show that, when compared with the existing high speed FIR designs such as the symmetric systolic form in [13] and the hybrid form in [1], the proposed form can achieve significant area and power savings with great ADP and PDP reduction. Moreover, when compared with the symmetric systolic form in [13] the required latency can be approximately reduced by 33.3%, which clearly shows the performance improvement of the proposed method.