{"title":"用于宽带信号处理的信道化前端,具有宽松的抗混叠滤波","authors":"V. Singh, Wei-Gi Ho, R. Gharpurey","doi":"10.1109/DCAS.2015.7356596","DOIUrl":null,"url":null,"abstract":"A digital post-processing approach for reducing the anti-aliasing requirement in a frequency-folding channelizer architecture is described. The channelizer decomposes a broadband spectrum into multiple sub-bands. A signal of bandwidth N/2fLO is downconverted into N paths that are clocked using rectangular, non-overlapping pulse waveforms at a fundamental frequency of fLO with a duty-cycle of 1/N. All portions of the input are aliased onto a baseband signal of bandwidth fLO/2, which is low-pass filtered and applied to N sub-ADCs with identical sampling clocks. Individual sub-bands are selected in the digital domain. Aliasing between sub-bands is also removed after digitization. This is used to reduce the order of the anti-aliasing filters in the analog signal paths, which can potentially reduce power and design complexity. It is shown that a filter-order of at least one is necessary in the analog-domain to apply digital post-processing. The approach is verified in simulation.","PeriodicalId":162311,"journal":{"name":"2015 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Channelized front-ends for broadband signal processing with relaxed anti-aliasing filtering\",\"authors\":\"V. Singh, Wei-Gi Ho, R. Gharpurey\",\"doi\":\"10.1109/DCAS.2015.7356596\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A digital post-processing approach for reducing the anti-aliasing requirement in a frequency-folding channelizer architecture is described. The channelizer decomposes a broadband spectrum into multiple sub-bands. A signal of bandwidth N/2fLO is downconverted into N paths that are clocked using rectangular, non-overlapping pulse waveforms at a fundamental frequency of fLO with a duty-cycle of 1/N. All portions of the input are aliased onto a baseband signal of bandwidth fLO/2, which is low-pass filtered and applied to N sub-ADCs with identical sampling clocks. Individual sub-bands are selected in the digital domain. Aliasing between sub-bands is also removed after digitization. This is used to reduce the order of the anti-aliasing filters in the analog signal paths, which can potentially reduce power and design complexity. It is shown that a filter-order of at least one is necessary in the analog-domain to apply digital post-processing. The approach is verified in simulation.\",\"PeriodicalId\":162311,\"journal\":{\"name\":\"2015 IEEE Dallas Circuits and Systems Conference (DCAS)\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Dallas Circuits and Systems Conference (DCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DCAS.2015.7356596\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Dallas Circuits and Systems Conference (DCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCAS.2015.7356596","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Channelized front-ends for broadband signal processing with relaxed anti-aliasing filtering
A digital post-processing approach for reducing the anti-aliasing requirement in a frequency-folding channelizer architecture is described. The channelizer decomposes a broadband spectrum into multiple sub-bands. A signal of bandwidth N/2fLO is downconverted into N paths that are clocked using rectangular, non-overlapping pulse waveforms at a fundamental frequency of fLO with a duty-cycle of 1/N. All portions of the input are aliased onto a baseband signal of bandwidth fLO/2, which is low-pass filtered and applied to N sub-ADCs with identical sampling clocks. Individual sub-bands are selected in the digital domain. Aliasing between sub-bands is also removed after digitization. This is used to reduce the order of the anti-aliasing filters in the analog signal paths, which can potentially reduce power and design complexity. It is shown that a filter-order of at least one is necessary in the analog-domain to apply digital post-processing. The approach is verified in simulation.