An alternative approach to design reconfigurable mixed signal VLSI DA based FIR filter

This paper presents an alternative approach to design reconfigurable mixed signal distributed arithmetic (DA) based finite impulse response (FIR) filter. The proposed architecture is based on the use of normal CMOS transistor for various computational blocks involved in the filter design. To maintain the reconfigurability, an electrically erasable programmable read only memory (EEPROM) based potentiometer (POT) is also employed that stores the analog filter weights. Moreover, the analog weights are separately added in last cycle corresponding to most significant bit and eliminates the extra control circuitry for bit-inversion. We have simulated the proposed architecture in UMC 180 nm CMOS using Cadence Spectre with input sampling frequency of 1.25 MHz. It is found that the proposed architecture dissipates the static power of 4.85 mW.