Effective Cache utilization in Multi-core Real Time Operating System

Cache memory has grown to be an essential component of CPU architecture due to the growing gap between processing power and main memory access latency. The cache design that processors use has numerous levels, with the smallest, fastest private caches (Level 1) supported to the largest, slowest caches (Level 2). Snoop Control Units (SCUs) have been added to multi-core processors to ensure the coherency of private cache data. The literature that is currently available discusses application-specific cache alignment methods. When inter-core communication begins to function at the OS level, Symmetric Multi-Processing (SMP)/Asymmetric Multi-Processing (AMP) Real Time Operating Systems (RTOS) will add a significant amount of overhead to system activities. This study is the first to propose an unique signalling technique between the cores based on cache aware information lookups. It is implemented as "SCHEDULE-ASSIST" and "ENTITY-ASSIST" in the Little Kernel scheduler, an SMP RTOS scheduler. We demonstrate an up to 13% improvement in RTOS processing Key Performance Indices (KPI) for RTOS’ Application Programming Interfaces (APIs) compared to schemes that are unaware of the cache design through analytical modelling and implementation using a Xilinx Evaluation Kit.