CPU引脚密度的研究及其应用

2018 IEEE Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity (EMC, SI & PI) Pub Date : 2018-07-01 DOI:10.1109/EMCSI.2018.8495252

Karen Navarro, R. Enriquez, A. Cueva, Clemens Thielen, B. Garcia, H. Peng

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引用次数: 0

摘要

本文介绍了3种高效DDR互连的新模式。这些模式针对封装引脚数量有限的情况进行了优化。对于所有情况，行业规范都是完整的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Study of CPU Pinout for Density and Its Application

This work introduces 3 new patterns for efficient DDR interconnection. The patterns are optimized for implementation where the number of package pins is limited. For all cases, the industry specifications are fullfiled.

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来源期刊

2018 IEEE Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity (EMC, SI & PI)

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