{"title":"一种2.0 ~ 3.0 GHz CMOS低噪声放大器及其应用","authors":"Ravinder Kumar, V. Srivastava","doi":"10.1109/NUICONE.2011.6153277","DOIUrl":null,"url":null,"abstract":"This paper presents a 2 GHz to 3 GHz Low Noise Amplifier (LNA) design based on a cascode topology. The proposed method is addressed to optimize noise performance and power efficiency while maintaining good input and output matching. This LNA has a measured power gain of 13.5dB and noise figure of 1.5 dB. The output insertion loss S22 is •9dB. input return loss (s11) is •22dB. The design simulation process is using Advance Design System (ADS) software and implemented in TSMC 0.18 µm CMOS technology with very low power dissipation.","PeriodicalId":206392,"journal":{"name":"2011 Nirma University International Conference on Engineering","volume":"56 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 2.0 to 3.0 GHz CMOS low noise amplifier and its applications\",\"authors\":\"Ravinder Kumar, V. Srivastava\",\"doi\":\"10.1109/NUICONE.2011.6153277\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 2 GHz to 3 GHz Low Noise Amplifier (LNA) design based on a cascode topology. The proposed method is addressed to optimize noise performance and power efficiency while maintaining good input and output matching. This LNA has a measured power gain of 13.5dB and noise figure of 1.5 dB. The output insertion loss S22 is •9dB. input return loss (s11) is •22dB. The design simulation process is using Advance Design System (ADS) software and implemented in TSMC 0.18 µm CMOS technology with very low power dissipation.\",\"PeriodicalId\":206392,\"journal\":{\"name\":\"2011 Nirma University International Conference on Engineering\",\"volume\":\"56 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 Nirma University International Conference on Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NUICONE.2011.6153277\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Nirma University International Conference on Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NUICONE.2011.6153277","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2.0 to 3.0 GHz CMOS low noise amplifier and its applications
This paper presents a 2 GHz to 3 GHz Low Noise Amplifier (LNA) design based on a cascode topology. The proposed method is addressed to optimize noise performance and power efficiency while maintaining good input and output matching. This LNA has a measured power gain of 13.5dB and noise figure of 1.5 dB. The output insertion loss S22 is •9dB. input return loss (s11) is •22dB. The design simulation process is using Advance Design System (ADS) software and implemented in TSMC 0.18 µm CMOS technology with very low power dissipation.
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