{"title":"IEEE P1581兼容设备的测试模式进入和退出方法","authors":"H. Ehrenberg","doi":"10.1109/TEST.2009.5355636","DOIUrl":null,"url":null,"abstract":"IEEE P1581 is aimed at ICs that are otherwise not provisioned with Design For Test (DFT) for any reason, targeting primarily memory devices, but also allowing for implementation in other devices. This Poster provides an overview of Test Mode Entry and Exit Methods proposed in IEEE P1581.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Test Mode Entry and Exit Methods for IEEE P1581 compliant devices\",\"authors\":\"H. Ehrenberg\",\"doi\":\"10.1109/TEST.2009.5355636\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"IEEE P1581 is aimed at ICs that are otherwise not provisioned with Design For Test (DFT) for any reason, targeting primarily memory devices, but also allowing for implementation in other devices. This Poster provides an overview of Test Mode Entry and Exit Methods proposed in IEEE P1581.\",\"PeriodicalId\":419063,\"journal\":{\"name\":\"2009 International Test Conference\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.2009.5355636\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2009.5355636","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Test Mode Entry and Exit Methods for IEEE P1581 compliant devices
IEEE P1581 is aimed at ICs that are otherwise not provisioned with Design For Test (DFT) for any reason, targeting primarily memory devices, but also allowing for implementation in other devices. This Poster provides an overview of Test Mode Entry and Exit Methods proposed in IEEE P1581.