{"title":"频率合成器的模式1 MB-OFDM UWB应用","authors":"Jung-Yu Chang, Che-Wei Fan, Shen-Iuan Liu","doi":"10.1109/VDAT.2009.5158134","DOIUrl":null,"url":null,"abstract":"A frequency synthesizer for Mode-1 MB-OFDM UWB applications is realized in 65nm CMOS. By using a delay-locked loop (DLL) and the proposed multiply-by-two circuit, the frequency synthesizer achieves the in-band spur of −40dBc for the three-band operation. The proposed multiply-by-2 circuit realizes the quadrature signals, and its input signals do not need the 50% duty cycle. A modified current-starving cell in a DLL is also proposed to reduce the supply noise sensitivity. The measured switching time from 3.342GHz to 4.488GHz is around 1.1ns. The area is 1.25×1.175mm2 with pads and the power is 19.2mW for 1.2V supply.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A frequency synthesizer for Mode-1 MB-OFDM UWB applications\",\"authors\":\"Jung-Yu Chang, Che-Wei Fan, Shen-Iuan Liu\",\"doi\":\"10.1109/VDAT.2009.5158134\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A frequency synthesizer for Mode-1 MB-OFDM UWB applications is realized in 65nm CMOS. By using a delay-locked loop (DLL) and the proposed multiply-by-two circuit, the frequency synthesizer achieves the in-band spur of −40dBc for the three-band operation. The proposed multiply-by-2 circuit realizes the quadrature signals, and its input signals do not need the 50% duty cycle. A modified current-starving cell in a DLL is also proposed to reduce the supply noise sensitivity. The measured switching time from 3.342GHz to 4.488GHz is around 1.1ns. The area is 1.25×1.175mm2 with pads and the power is 19.2mW for 1.2V supply.\",\"PeriodicalId\":246670,\"journal\":{\"name\":\"2009 International Symposium on VLSI Design, Automation and Test\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Symposium on VLSI Design, Automation and Test\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2009.5158134\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2009.5158134","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A frequency synthesizer for Mode-1 MB-OFDM UWB applications
A frequency synthesizer for Mode-1 MB-OFDM UWB applications is realized in 65nm CMOS. By using a delay-locked loop (DLL) and the proposed multiply-by-two circuit, the frequency synthesizer achieves the in-band spur of −40dBc for the three-band operation. The proposed multiply-by-2 circuit realizes the quadrature signals, and its input signals do not need the 50% duty cycle. A modified current-starving cell in a DLL is also proposed to reduce the supply noise sensitivity. The measured switching time from 3.342GHz to 4.488GHz is around 1.1ns. The area is 1.25×1.175mm2 with pads and the power is 19.2mW for 1.2V supply.
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