{"title":"利用DEv-PROMELA进行软件建模与验证","authors":"Aznam Yacoub, M. Hamri, C. Frydman","doi":"10.1145/2901378.2901388","DOIUrl":null,"url":null,"abstract":"Efficient modelling and verification of models need an accurate representation of systems. Especially, PROMELA cannot represent time as quantitative properties. That means some properties depending on time cannot be checked with SPIN model-checker. Discrete-Time approaches and dense representation of time were successfully introduced in SPIN as extensions but suffer of the expected statespace explosion problem. Another approach using discrete-event representation of time and simulation has been proposed to minimize this statespace explosion problem. In this paper, we show how this extension, DEv-PROMELA, can be used in order to model and verify software designs by combining simulation and formal verification.","PeriodicalId":325258,"journal":{"name":"Proceedings of the 2016 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Using DEv-PROMELA for Modelling and Verification of Software\",\"authors\":\"Aznam Yacoub, M. Hamri, C. Frydman\",\"doi\":\"10.1145/2901378.2901388\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Efficient modelling and verification of models need an accurate representation of systems. Especially, PROMELA cannot represent time as quantitative properties. That means some properties depending on time cannot be checked with SPIN model-checker. Discrete-Time approaches and dense representation of time were successfully introduced in SPIN as extensions but suffer of the expected statespace explosion problem. Another approach using discrete-event representation of time and simulation has been proposed to minimize this statespace explosion problem. In this paper, we show how this extension, DEv-PROMELA, can be used in order to model and verify software designs by combining simulation and formal verification.\",\"PeriodicalId\":325258,\"journal\":{\"name\":\"Proceedings of the 2016 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2016 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/2901378.2901388\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2016 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2901378.2901388","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Using DEv-PROMELA for Modelling and Verification of Software
Efficient modelling and verification of models need an accurate representation of systems. Especially, PROMELA cannot represent time as quantitative properties. That means some properties depending on time cannot be checked with SPIN model-checker. Discrete-Time approaches and dense representation of time were successfully introduced in SPIN as extensions but suffer of the expected statespace explosion problem. Another approach using discrete-event representation of time and simulation has been proposed to minimize this statespace explosion problem. In this paper, we show how this extension, DEv-PROMELA, can be used in order to model and verify software designs by combining simulation and formal verification.