{"title":"超高频RFID应用的标准CMOS电压倍增器架构:研究和实现","authors":"E. Bergeret, J. Gaubert, P. Pannier","doi":"10.1109/RFID.2007.346158","DOIUrl":null,"url":null,"abstract":"An analysis of RFID multipliers architectures is presented. An analytic model of classical Mosfet multiplier is given, which permits to determine the main design parameters of this kind of circuit and their impacts on efficiency. Thanks to this study a new architecture is proposed in order to increase efficiency. The two multipliers are designed and implemented in the same standard 0.18 mum CMOS process. Measurements have been done and show functionality of the multipliers and improvement between the architectures.","PeriodicalId":369499,"journal":{"name":"2007 IEEE International Conference on RFID","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Standard CMOS voltage multipliers architectures for UHF RFID applications : study and implementation\",\"authors\":\"E. Bergeret, J. Gaubert, P. Pannier\",\"doi\":\"10.1109/RFID.2007.346158\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An analysis of RFID multipliers architectures is presented. An analytic model of classical Mosfet multiplier is given, which permits to determine the main design parameters of this kind of circuit and their impacts on efficiency. Thanks to this study a new architecture is proposed in order to increase efficiency. The two multipliers are designed and implemented in the same standard 0.18 mum CMOS process. Measurements have been done and show functionality of the multipliers and improvement between the architectures.\",\"PeriodicalId\":369499,\"journal\":{\"name\":\"2007 IEEE International Conference on RFID\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-03-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE International Conference on RFID\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFID.2007.346158\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE International Conference on RFID","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFID.2007.346158","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
摘要
对RFID乘法器的结构进行了分析。给出了经典Mosfet乘法器的解析模型，从而确定了该类电路的主要设计参数及其对效率的影响。在此基础上，提出了一种新的架构，以提高效率。这两个乘法器在相同的标准0.18 μ m CMOS工艺中设计和实现。测量已经完成，并显示了乘数器的功能和架构之间的改进。
Standard CMOS voltage multipliers architectures for UHF RFID applications : study and implementation
An analysis of RFID multipliers architectures is presented. An analytic model of classical Mosfet multiplier is given, which permits to determine the main design parameters of this kind of circuit and their impacts on efficiency. Thanks to this study a new architecture is proposed in order to increase efficiency. The two multipliers are designed and implemented in the same standard 0.18 mum CMOS process. Measurements have been done and show functionality of the multipliers and improvement between the architectures.
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