Design and Simulation of Evolvable Hardware for Image Processing

The paper describes the design of an image processing system which is evolvable and self-reconfigurable The evolutionary algorithm chosen is genetic algorithm. Existing hardware filter schemes based on evolutionary principles compute Mean Absolute Error or Peak Signal to Noise Ratio for fitness calculation. The proposed scheme makes use of entropy based noise detection and estimation scheme as fitness indicator. With this feature, the system can function even in the absence of a noise-free image reference. Quality and generality of the scheme is demonstrated. The design is planned to be implemented on FPGA platform for reconfigurability and adaptability. Due to the complexity in the design and implementation of the system, a well thought-out design flow is followed. MATLAB based functional simulation and verification is carried out first, followed by System On Chip implementation. Exhaustive simulations and design trade off studies were conducted to verify proof of concept. Validation results prove versatility and robustness of the scheme.