采用高漏电CMOS工艺设计的1 V锁相环，工作频率为10-700 MHz

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992223

R. Holzer

{"title":"采用高漏电CMOS工艺设计的1 V锁相环，工作频率为10-700 MHz","authors":"R. Holzer","doi":"10.1109/ISSCC.2002.992223","DOIUrl":null,"url":null,"abstract":"A PLL is fabricated in a 0.13 /spl mu/m logic process where leakage currents are high. The loop capacitor is implemented by a structure of poly and 9 metal layers. The VCO is implemented with common-mode feedback to compensate for leakage currents. Maximum VCO frequency is 1400 MHz. Typical power is 7 mW at 200 MHz. RMS jitter is 25.4 ps at 360 MHz.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"29","resultStr":"{\"title\":\"A 1 V CMOS PLL designed in high-leakage CMOS process operating at 10-700 MHz\",\"authors\":\"R. Holzer\",\"doi\":\"10.1109/ISSCC.2002.992223\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A PLL is fabricated in a 0.13 /spl mu/m logic process where leakage currents are high. The loop capacitor is implemented by a structure of poly and 9 metal layers. The VCO is implemented with common-mode feedback to compensate for leakage currents. Maximum VCO frequency is 1400 MHz. Typical power is 7 mW at 200 MHz. RMS jitter is 25.4 ps at 360 MHz.\",\"PeriodicalId\":423674,\"journal\":{\"name\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"29\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2002.992223\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.992223","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 29

摘要

锁相环以0.13 /spl mu/m的逻辑工艺制作，漏电流高。环路电容器由聚层和9层金属层结构实现。该压控振荡器采用共模反馈来补偿泄漏电流。最大压控振荡器频率为1400mhz。在200mhz时，典型功率为7mw。在360兆赫时，RMS抖动为25.4 ps。

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A 1 V CMOS PLL designed in high-leakage CMOS process operating at 10-700 MHz

A PLL is fabricated in a 0.13 /spl mu/m logic process where leakage currents are high. The loop capacitor is implemented by a structure of poly and 9 metal layers. The VCO is implemented with common-mode feedback to compensate for leakage currents. Maximum VCO frequency is 1400 MHz. Typical power is 7 mW at 200 MHz. RMS jitter is 25.4 ps at 360 MHz.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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