A method for quick estimation of optimum bulk bias voltages for SoC designs

A method for early estimation of optimum bulk bias potential is proposed. The suggested strategy removes the requirement for synthesis based exploration, greatly reducing Turn Around Time (TAT). As the core of the method, we present a linear model for estimating the Energy Delay Product (EDP), which relies on characterization of Static and Dynamic Energy, as well as Delay for a single Inverter cell under different bulk bias operating conditions. This model weights these vectors using design constraint parameters such as switching activity and clock period. We have validated the model by means of statistical analysis. The method was then tested by comparison of Quality of Results (QoR) obtained from implementation of an open source System on a Chip (SoC) design, first using our predicted bias voltages and then using an estimate of the optimum found by exploration over a post layout annotated Netlist. Our method has achieved a 6.3% of improvement on EDP with a very low TAT.