{"title":"一种简单且具有成本效益的双面光刻校准工艺,采用单掩模和直写双曝光工艺的组合","authors":"Goutam Prakash, Vasanth Kumar, Sabiha Sultana","doi":"10.1109/ICEE56203.2022.10117867","DOIUrl":null,"url":null,"abstract":"In this work, we present a discussion on an efficient and economical ‘Double Exposure’ (dual exposure or multiple exposures) method to achieve lithographic pattern alignments on opposite sides of various substrates (Silicon, GaN, GaAs, SiN) using Direct Writing tools and a single (standard) alignment marker photo mask. By exposing and developing the same photoresist (PR) multiple times, while using the corresponding lithographic tools in concert, the efficiency can be significantly improved while drastically reducing the resource cost with no compromise in the final resolution. The process has been optimized and demonstrated for repeatability in the lithography step followed by both etching and/or deposition (lift-off) processes. The proposed process is especially beneficial in the Backside Alignment (BSA) of Single- Side Polished (SSP) Silicon wafers. This has also been proven for BSA applications in full-fledged process flows for MEMS/NEMS and Heterogeneously-Integrated Devices.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A simple and cost-effective dual side lithography alignment process using a combination of a single mask and direct writing Double Exposure process\",\"authors\":\"Goutam Prakash, Vasanth Kumar, Sabiha Sultana\",\"doi\":\"10.1109/ICEE56203.2022.10117867\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, we present a discussion on an efficient and economical ‘Double Exposure’ (dual exposure or multiple exposures) method to achieve lithographic pattern alignments on opposite sides of various substrates (Silicon, GaN, GaAs, SiN) using Direct Writing tools and a single (standard) alignment marker photo mask. By exposing and developing the same photoresist (PR) multiple times, while using the corresponding lithographic tools in concert, the efficiency can be significantly improved while drastically reducing the resource cost with no compromise in the final resolution. The process has been optimized and demonstrated for repeatability in the lithography step followed by both etching and/or deposition (lift-off) processes. The proposed process is especially beneficial in the Backside Alignment (BSA) of Single- Side Polished (SSP) Silicon wafers. This has also been proven for BSA applications in full-fledged process flows for MEMS/NEMS and Heterogeneously-Integrated Devices.\",\"PeriodicalId\":281727,\"journal\":{\"name\":\"2022 IEEE International Conference on Emerging Electronics (ICEE)\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Conference on Emerging Electronics (ICEE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEE56203.2022.10117867\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Emerging Electronics (ICEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEE56203.2022.10117867","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A simple and cost-effective dual side lithography alignment process using a combination of a single mask and direct writing Double Exposure process
In this work, we present a discussion on an efficient and economical ‘Double Exposure’ (dual exposure or multiple exposures) method to achieve lithographic pattern alignments on opposite sides of various substrates (Silicon, GaN, GaAs, SiN) using Direct Writing tools and a single (standard) alignment marker photo mask. By exposing and developing the same photoresist (PR) multiple times, while using the corresponding lithographic tools in concert, the efficiency can be significantly improved while drastically reducing the resource cost with no compromise in the final resolution. The process has been optimized and demonstrated for repeatability in the lithography step followed by both etching and/or deposition (lift-off) processes. The proposed process is especially beneficial in the Backside Alignment (BSA) of Single- Side Polished (SSP) Silicon wafers. This has also been proven for BSA applications in full-fledged process flows for MEMS/NEMS and Heterogeneously-Integrated Devices.