Alain J. Martin, Andrew Lines, R. Manohar, M. Nyström, P. Pénzes, Robert Southworth, U. Cummings
{"title":"一种异步MIPS R3000微处理器的设计","authors":"Alain J. Martin, Andrew Lines, R. Manohar, M. Nyström, P. Pénzes, Robert Southworth, U. Cummings","doi":"10.1109/ARVLSI.1997.634853","DOIUrl":null,"url":null,"abstract":"The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0.6 /spl mu/m CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 W. The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high throughput.","PeriodicalId":201675,"journal":{"name":"Proceedings Seventeenth Conference on Advanced Research in VLSI","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"337","resultStr":"{\"title\":\"The design of an asynchronous MIPS R3000 microprocessor\",\"authors\":\"Alain J. Martin, Andrew Lines, R. Manohar, M. Nyström, P. Pénzes, Robert Southworth, U. Cummings\",\"doi\":\"10.1109/ARVLSI.1997.634853\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0.6 /spl mu/m CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 W. The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high throughput.\",\"PeriodicalId\":201675,\"journal\":{\"name\":\"Proceedings Seventeenth Conference on Advanced Research in VLSI\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"337\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Seventeenth Conference on Advanced Research in VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARVLSI.1997.634853\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Seventeenth Conference on Advanced Research in VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARVLSI.1997.634853","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The design of an asynchronous MIPS R3000 microprocessor
The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0.6 /spl mu/m CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 W. The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high throughput.
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