提高锁频范围的全数字锁相环设计

2019 2nd International Conference on Signal Processing and Communication (ICSPC) Pub Date : 2019-03-01 DOI:10.1109/ICSPC46172.2019.8976793

Anjeleena Erm, Nidhi Toppo, D. Sugumar, P. Vanathi

{"title":"提高锁频范围的全数字锁相环设计","authors":"Anjeleena Erm, Nidhi Toppo, D. Sugumar, P. Vanathi","doi":"10.1109/ICSPC46172.2019.8976793","DOIUrl":null,"url":null,"abstract":"This paper presents the design and implementation of All Digital Phase Locked Loop (ADPLL) for improved lock range. FPGA implementation of improvised ADPLL is carried out on Xilinx Artix-7(xc7alStcpg236-1) chip. The modified work is carried out for 200 KHz central frequency(fo) under complete digitalization. It provides a frequency lock range of 177 KHz to 222 KHz with Lock time of 12.57us and power consumption 0.088W under delay of 0.8 ns. This modified design, outputs an increase in Operational frequency range compared to previous design under low frequency.","PeriodicalId":321652,"journal":{"name":"2019 2nd International Conference on Signal Processing and Communication (ICSPC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of All-Digital Phase Locked Loop for Improved Frequency Lock Range\",\"authors\":\"Anjeleena Erm, Nidhi Toppo, D. Sugumar, P. Vanathi\",\"doi\":\"10.1109/ICSPC46172.2019.8976793\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design and implementation of All Digital Phase Locked Loop (ADPLL) for improved lock range. FPGA implementation of improvised ADPLL is carried out on Xilinx Artix-7(xc7alStcpg236-1) chip. The modified work is carried out for 200 KHz central frequency(fo) under complete digitalization. It provides a frequency lock range of 177 KHz to 222 KHz with Lock time of 12.57us and power consumption 0.088W under delay of 0.8 ns. This modified design, outputs an increase in Operational frequency range compared to previous design under low frequency.\",\"PeriodicalId\":321652,\"journal\":{\"name\":\"2019 2nd International Conference on Signal Processing and Communication (ICSPC)\",\"volume\":\"74 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 2nd International Conference on Signal Processing and Communication (ICSPC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSPC46172.2019.8976793\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 2nd International Conference on Signal Processing and Communication (ICSPC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSPC46172.2019.8976793","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文提出了提高锁相范围的全数字锁相环的设计与实现。在Xilinx Artix-7(xc7alStcpg236-1)芯片上进行了简易ADPLL的FPGA实现。在完全数字化的情况下，对200 KHz的中心频率进行了改进工作。它提供的频率锁定范围为177 KHz至222 KHz，锁定时间为12.57us，功耗为0.088W，延迟为0.8 ns。这种改进的设计在低频下输出的工作频率范围比以前的设计大。

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Design of All-Digital Phase Locked Loop for Improved Frequency Lock Range

This paper presents the design and implementation of All Digital Phase Locked Loop (ADPLL) for improved lock range. FPGA implementation of improvised ADPLL is carried out on Xilinx Artix-7(xc7alStcpg236-1) chip. The modified work is carried out for 200 KHz central frequency(fo) under complete digitalization. It provides a frequency lock range of 177 KHz to 222 KHz with Lock time of 12.57us and power consumption 0.088W under delay of 0.8 ns. This modified design, outputs an increase in Operational frequency range compared to previous design under low frequency.

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2019 2nd International Conference on Signal Processing and Communication (ICSPC)

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