VLSI implementation of a fully parallel stochastic neural network

Presents a purely digital stochastic implementation of multilayer neural networks. The authors have developed this implementation using an architecture that permits the addition of a very large number of synaptic connections, provided that the neuron's transfer function is the hard limiting function. The expression that relates the design parameter, that is, the maximum pulse density, with the accuracy of the operations has been used as the design criterion. The resulting circuit is easily configurable and expandable.<>