{"title":"用于PAM接收机的8gbps快速锁定自动增益控制","authors":"Guo-Wei Wu, Wei-Zen Chen, Shih-Hao Huang","doi":"10.1109/ASSCC.2009.5357153","DOIUrl":null,"url":null,"abstract":"An 8 Gbps automatic gain control (AGC) loop for PAM receiver is proposed. Incorporating digital intensive gain control scheme, the dynamic range of the variable gain amplifier is 22 dB with a resolution of 0.9 dB/step. The locking time of the AGC loop is less than 200 ns and independent of input amplitude. Fabricated in a 0.18 μm CMOS technology, the chip size is 0.62 mm × 0.62 mm. The total power dissipation is 84 mW from a 1.8 V supply.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"An 8 Gbps fast-locked automatic gain control for PAM receiver\",\"authors\":\"Guo-Wei Wu, Wei-Zen Chen, Shih-Hao Huang\",\"doi\":\"10.1109/ASSCC.2009.5357153\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An 8 Gbps automatic gain control (AGC) loop for PAM receiver is proposed. Incorporating digital intensive gain control scheme, the dynamic range of the variable gain amplifier is 22 dB with a resolution of 0.9 dB/step. The locking time of the AGC loop is less than 200 ns and independent of input amplitude. Fabricated in a 0.18 μm CMOS technology, the chip size is 0.62 mm × 0.62 mm. The total power dissipation is 84 mW from a 1.8 V supply.\",\"PeriodicalId\":263023,\"journal\":{\"name\":\"2009 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2009.5357153\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2009.5357153","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 8 Gbps fast-locked automatic gain control for PAM receiver
An 8 Gbps automatic gain control (AGC) loop for PAM receiver is proposed. Incorporating digital intensive gain control scheme, the dynamic range of the variable gain amplifier is 22 dB with a resolution of 0.9 dB/step. The locking time of the AGC loop is less than 200 ns and independent of input amplitude. Fabricated in a 0.18 μm CMOS technology, the chip size is 0.62 mm × 0.62 mm. The total power dissipation is 84 mW from a 1.8 V supply.
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