{"title":"25ghz静态分频器和25gb /s多路复用器,采用0.12 /spl mu/m CMOS","authors":"H. Knapp, H. Wohlmuth, M. Wurzer, M. Rest","doi":"10.1109/ISSCC.2002.993052","DOIUrl":null,"url":null,"abstract":"A static 2:1 frequency divider operating up to 25.4 GHz at 41 mA and a 25 Gb/s 2:1 multiplexer at 29 mA implemented in current-mode logic have differential 50 /spl Omega/ inputs and outputs. They are fabricated in a 0.12 /spl mu/m CMOS process and operate from a 1.5 V supply.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"25 GHz static frequency divider and 25 Gb/s multiplexer in 0.12 /spl mu/m CMOS\",\"authors\":\"H. Knapp, H. Wohlmuth, M. Wurzer, M. Rest\",\"doi\":\"10.1109/ISSCC.2002.993052\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A static 2:1 frequency divider operating up to 25.4 GHz at 41 mA and a 25 Gb/s 2:1 multiplexer at 29 mA implemented in current-mode logic have differential 50 /spl Omega/ inputs and outputs. They are fabricated in a 0.12 /spl mu/m CMOS process and operate from a 1.5 V supply.\",\"PeriodicalId\":423674,\"journal\":{\"name\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"volume\":\"67 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2002.993052\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.993052","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
25 GHz static frequency divider and 25 Gb/s multiplexer in 0.12 /spl mu/m CMOS
A static 2:1 frequency divider operating up to 25.4 GHz at 41 mA and a 25 Gb/s 2:1 multiplexer at 29 mA implemented in current-mode logic have differential 50 /spl Omega/ inputs and outputs. They are fabricated in a 0.12 /spl mu/m CMOS process and operate from a 1.5 V supply.