智能电源混合集成电路中寄生双极衬底耦合导致的带隙失效研究

V. Tomasevic, A. Boyer, S. Bendhia
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引用次数: 3

摘要

为了以具有竞争力的成本在同一芯片上合并低功耗和高压器件,智能电源集成电路(ic)得到了广泛的应用。在智能电源集成电路中,低功率和高压器件的存在导致开关功率级和敏感模拟模块之间的寄生衬底相互作用。这是目前智能电源集成电路失效的主要原因,引起昂贵的电路重新设计。现代CAD工具不能准确地模拟这种相互作用,这种相互作用表现为基材中少数载流子的注入及其在基材中的传播。为了在创新的CAD工具中创建电路设计,建模和实现之间的联系,需要通过测量激活寄生结构的高压扰动来验证这些模型。本文研究了智能功率集成电路中由大功率器件引起的衬底耦合引起的带隙失效问题,这种带隙失效会激活衬底内的寄生双极结构。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Bandgap failure study due to parasitic bipolar substrate coupling in Smart Power mixed ICs
In order to merge low power and high voltage devices on the same chip at competitive cost, Smart Power integrated circuits (ICs) are extensively used. The presence of low power and high voltage devices in Smart Power ICs cause parasitic substrate interaction between switched power stages and sensitive analog blocks. Nowadays this is the major cause of failure of Smart Power ICs inducing costly circuit redesign. Modern CAD tools cannot accurately simulate this type of interaction expressed as an injection of minority carriers in the substrate and their propagation in the substrate. In order to create a link between circuit design, modelling and implementation in innovative CAD tools there is a need to validate these models by measuring the high voltage perturbations that activate parasitic structures. This paper presents a study of bandgap failure issues due to the substrate coupling induced by high power parts of the circuit which can activate parasitic bipolar structures inside the substrate of Smart Power ICs.
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