{"title":"各种纳米技术:在45nm和130nm采用FS-GDI方法实现Alu的硬件复杂度较低","authors":"M. El-Bendary, M. Ayman","doi":"10.18642/ijamml_7100122186","DOIUrl":null,"url":null,"abstract":"Full Swing Gate Diffusion Input (FS-GDI) approach is power effective approach for realizing the different logic gates. In this research, this approach is utilized for realizing different four ALU design using 45nm and 130nm technologies. Also, the different low power VLSI logic styles and related past works are discussed with considering the 45nm and 65nm technologies for implementing various circuits for studying the technology size impact. The performance of the proposed ALU design is evaluated through power consumption, propagation delay and number of transistors. The variation of the ALU performance due to the used 45nm and 130nm technologies has been studied. The simulation is carried out utilizing Cadence Virtuoso simulator. The simulation experiments revealed the energy of the 4-bit ALU reduced by 32% compared to CMOS-based design and area of the digital circuits reducing. Regarding the different nano technologies, 45nm technology provides lower power consumption and delay time deceasing compared to ALU unit by 130nm technology. The presented approach of low hardware complexity achieves simplicity of the required ALU hardware through reducing the number of transistors.","PeriodicalId":405830,"journal":{"name":"International Journal of Applied Mathematics and Machine Learning","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Various Nano-Scale Technologies: Lower Hardware Complexity of Alu Realizing Utilizing FS-GDI Approach IN 45nm AND 130nm\",\"authors\":\"M. El-Bendary, M. Ayman\",\"doi\":\"10.18642/ijamml_7100122186\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Full Swing Gate Diffusion Input (FS-GDI) approach is power effective approach for realizing the different logic gates. In this research, this approach is utilized for realizing different four ALU design using 45nm and 130nm technologies. Also, the different low power VLSI logic styles and related past works are discussed with considering the 45nm and 65nm technologies for implementing various circuits for studying the technology size impact. The performance of the proposed ALU design is evaluated through power consumption, propagation delay and number of transistors. The variation of the ALU performance due to the used 45nm and 130nm technologies has been studied. The simulation is carried out utilizing Cadence Virtuoso simulator. The simulation experiments revealed the energy of the 4-bit ALU reduced by 32% compared to CMOS-based design and area of the digital circuits reducing. Regarding the different nano technologies, 45nm technology provides lower power consumption and delay time deceasing compared to ALU unit by 130nm technology. The presented approach of low hardware complexity achieves simplicity of the required ALU hardware through reducing the number of transistors.\",\"PeriodicalId\":405830,\"journal\":{\"name\":\"International Journal of Applied Mathematics and Machine Learning\",\"volume\":\"50 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-04-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Journal of Applied Mathematics and Machine Learning\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.18642/ijamml_7100122186\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Applied Mathematics and Machine Learning","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.18642/ijamml_7100122186","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
Full - Swing门扩散输入(FS-GDI)方法是实现不同逻辑门的有效方法。在本研究中,利用该方法实现了45纳米和130纳米技术的不同四ALU设计。此外,还讨论了不同的低功耗VLSI逻辑风格和相关的过去工作,并考虑了45纳米和65纳米技术实现各种电路,以研究技术尺寸的影响。通过功耗、传输延迟和晶体管数量来评估所提出的ALU设计的性能。研究了45纳米和130纳米工艺对ALU性能的影响。利用Cadence Virtuoso模拟器进行仿真。仿真实验表明,与基于cmos的设计相比,4位ALU的能量降低了32%,数字电路的面积也减小了。在不同的纳米技术中,45nm技术比130nm技术提供更低的功耗和延迟时间。所提出的低硬件复杂度的方法通过减少晶体管的数量来实现所需ALU硬件的简化。
Various Nano-Scale Technologies: Lower Hardware Complexity of Alu Realizing Utilizing FS-GDI Approach IN 45nm AND 130nm
Full Swing Gate Diffusion Input (FS-GDI) approach is power effective approach for realizing the different logic gates. In this research, this approach is utilized for realizing different four ALU design using 45nm and 130nm technologies. Also, the different low power VLSI logic styles and related past works are discussed with considering the 45nm and 65nm technologies for implementing various circuits for studying the technology size impact. The performance of the proposed ALU design is evaluated through power consumption, propagation delay and number of transistors. The variation of the ALU performance due to the used 45nm and 130nm technologies has been studied. The simulation is carried out utilizing Cadence Virtuoso simulator. The simulation experiments revealed the energy of the 4-bit ALU reduced by 32% compared to CMOS-based design and area of the digital circuits reducing. Regarding the different nano technologies, 45nm technology provides lower power consumption and delay time deceasing compared to ALU unit by 130nm technology. The presented approach of low hardware complexity achieves simplicity of the required ALU hardware through reducing the number of transistors.