Design and Implementation of a Digital Radar Pulse Receiver on FPGA

Signal generation and detection are key elements in designing and testing a radar system. In order to detect objects effectively and accurately, filtering is needed to reduce the amount of noise that comes from the surrounding environment, which is then deinterleaved based on their Pulse Descriptor Words (PDW). Deinterleaving is the process of separating signals that are interleaved together. This paper presents the design and implementation of a digital radar pulse receiver on the Zynq UltraScale+ MPSoC ZCU104 FPGA board. The AD-FMCOMMS2-EBZ RF module was attached to the Zync UltraScale+ MPSoc ZCU104 FPGA board to allow it to send and receive data. The data can be transmitted and received using antennas or data cables. To send and receive, two sets of FPGA and RF modules were necessary. One transmitted and the other would receive.