{"title":"建立一个测试环境组件在VHDL的红外链路访问协议(IrLAP)兼容的ASIC接口","authors":"M. D. McKinney","doi":"10.1109/VIUF.1997.623953","DOIUrl":null,"url":null,"abstract":"This paper presents the experiences of the Texas Instruments Bus Solutions ASIC design team in its efforts to create and use a component written in VHDL which was embedded into the test environment for an ASIC. The VHDL component described had to be: dynamically controllable; able to accept and check a wide range of expected results from the ASIC design; able to stimulate the design in every action which was compliant with the IrLAP specification; and able to inject several different kinds of errors into the stimulus flow under user control. Embedding this level of stimulus strength, self-checking and user control was a challenge, but completing the component allowed the ASIC design team to field a fully verified interface which has needed no changes since its release to silicon.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Building a test environment component in VHDL for an infrared link access protocol (IrLAP) compliant ASIC interface\",\"authors\":\"M. D. McKinney\",\"doi\":\"10.1109/VIUF.1997.623953\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the experiences of the Texas Instruments Bus Solutions ASIC design team in its efforts to create and use a component written in VHDL which was embedded into the test environment for an ASIC. The VHDL component described had to be: dynamically controllable; able to accept and check a wide range of expected results from the ASIC design; able to stimulate the design in every action which was compliant with the IrLAP specification; and able to inject several different kinds of errors into the stimulus flow under user control. Embedding this level of stimulus strength, self-checking and user control was a challenge, but completing the component allowed the ASIC design team to field a fully verified interface which has needed no changes since its release to silicon.\",\"PeriodicalId\":212876,\"journal\":{\"name\":\"Proceedings VHDL International Users' Forum. Fall Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-10-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings VHDL International Users' Forum. Fall Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VIUF.1997.623953\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings VHDL International Users' Forum. Fall Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VIUF.1997.623953","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Building a test environment component in VHDL for an infrared link access protocol (IrLAP) compliant ASIC interface
This paper presents the experiences of the Texas Instruments Bus Solutions ASIC design team in its efforts to create and use a component written in VHDL which was embedded into the test environment for an ASIC. The VHDL component described had to be: dynamically controllable; able to accept and check a wide range of expected results from the ASIC design; able to stimulate the design in every action which was compliant with the IrLAP specification; and able to inject several different kinds of errors into the stimulus flow under user control. Embedding this level of stimulus strength, self-checking and user control was a challenge, but completing the component allowed the ASIC design team to field a fully verified interface which has needed no changes since its release to silicon.