{"title":"基于noc的H.264解码器的系统级建模","authors":"A. Agarwal, C. Iskander, H. Kalva, R. Shankar","doi":"10.1109/SYSTEMS.2008.4519008","DOIUrl":null,"url":null,"abstract":"Networks-on-chip (NoC) are expected to play a key role in future embedded systems. A NoC-based system has the potential to support concurrent processing, in both software and hardware. This can however lead to concurrency issues. We present a multiprocessor system modeling and performance evaluation approach that addresses concurrency. We illustrate our methodology by mapping a H.264 decoder onto a 4 x 3 mesh- based NoC architecture. We show latency, area, and power consumption results for this NoC architecture abstracted from its FPGA implementation.","PeriodicalId":403208,"journal":{"name":"2008 2nd Annual IEEE Systems Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"System-Level Modeling of a NoC-Based H.264 Decoder\",\"authors\":\"A. Agarwal, C. Iskander, H. Kalva, R. Shankar\",\"doi\":\"10.1109/SYSTEMS.2008.4519008\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Networks-on-chip (NoC) are expected to play a key role in future embedded systems. A NoC-based system has the potential to support concurrent processing, in both software and hardware. This can however lead to concurrency issues. We present a multiprocessor system modeling and performance evaluation approach that addresses concurrency. We illustrate our methodology by mapping a H.264 decoder onto a 4 x 3 mesh- based NoC architecture. We show latency, area, and power consumption results for this NoC architecture abstracted from its FPGA implementation.\",\"PeriodicalId\":403208,\"journal\":{\"name\":\"2008 2nd Annual IEEE Systems Conference\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-04-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 2nd Annual IEEE Systems Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SYSTEMS.2008.4519008\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 2nd Annual IEEE Systems Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SYSTEMS.2008.4519008","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
System-Level Modeling of a NoC-Based H.264 Decoder
Networks-on-chip (NoC) are expected to play a key role in future embedded systems. A NoC-based system has the potential to support concurrent processing, in both software and hardware. This can however lead to concurrency issues. We present a multiprocessor system modeling and performance evaluation approach that addresses concurrency. We illustrate our methodology by mapping a H.264 decoder onto a 4 x 3 mesh- based NoC architecture. We show latency, area, and power consumption results for this NoC architecture abstracted from its FPGA implementation.
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