通过3-D集成为值得信赖的系统提供硬件支持

Jonathan Valamehr, Mohit Tiwari, T. Sherwood, R. Kastner, Ted Huffmire, C. Irvine, T. Levin
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引用次数: 23

摘要

硬件资源丰富;最先进的处理器拥有超过10亿个晶体管。然而,由于各种原因,用于高保证处理的专用硬件功能很少集成到这些商用处理器中(即,二十多年来每个供应商的几个功能),尽管最近有一些小的混乱(例如,ARM TrustZone, Intel VT-x/VT-d和AMD- v /AMD- vi, Intel TXT和AMD SVM,以及Intel AES-NI)。此外,随着芯片复杂性的增加,由于广泛的片上资源共享和缺乏相应的保护机制,敏感信息的可信处理变得越来越难以实现。在本文中,我们介绍了一种方法来提高商品集成电路的安全性,使用微小的修改,结合一个单独的集成电路,可以提供监控,访问控制,和其他有用的安全功能。我们引入了一个使用独立控制平面的新架构,使用3D集成堆叠,它允许专用安全机制的功能和经济,而不是单独从协处理器中获得,与底层商品计算硬件集成。我们首先描述了一种通过附加一个可选的控制平面来修改主机计算平面的一般方法。在一个开发的示例中,我们展示了这种方法如何通过将来自计算平面的信号路由到3-D控制平面的缓存监视器来减轻基于缓存的侧信道问题,从而提高系统的可信度。我们的示例应用程序在面积、延迟和性能影响方面的开销可以忽略不计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Hardware assistance for trustworthy systems through 3-D integration
Hardware resources are abundant; state-of-the-art processors have over one billion transistors. Yet for a variety of reasons, specialized hardware functions for high assurance processing are seldom (i.e., a couple of features per vendor over twenty years) integrated into these commodity processors, despite a small flurry of late (e.g., ARM TrustZone, Intel VT-x/VT-d and AMD-V/AMD-Vi, Intel TXT and AMD SVM, and Intel AES-NI). Furthermore, as chips increase in complexity, trustworthy processing of sensitive information can become increasingly difficult to achieve due to extensive on-chip resource sharing and the lack of corresponding protection mechanisms. In this paper, we introduce a method to enhance the security of commodity integrated circuits, using minor modifications, in conjunction with a separate integrated circuit that can provide monitoring, access control, and other useful security functions. We introduce a new architecture using a separate control plane, stacked using 3D integration, that allows for the function and economics of specialized security mechanisms, not available from a co-processor alone, to be integrated with the underlying commodity computing hardware. We first describe a general methodology to modify the host computation plane by attaching an optional control plane using 3-D integration. In a developed example we show how this approach can increase system trustworthiness, through mitigating the cache-based side channel problem by routing signals from the computation plane through a cache monitor in the 3-D control plane. We show that the overhead of our example application, in terms of area, delay and performance impact, is negligible.
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