FPGA Implementation of a Pseudo-Random Signal Generator for RF Hardware Test and Evaluation

Test and evaluation (T&E) is a critically important step before in-the-field deployment of radio frequency hardware in order to assure that the hardware meets its design requirements and specifications. Typically, T&E is performed either in a lab setting utilizing a software simulation environment or through real-world field testing. While the former approach is typically limited by the accuracy of the simulation models (of the anticipated hardware effects, channel conditions, etc.) and by non-real-time data rates, the latter can be extremely costly in terms of time, money, and manpower. To address these issues, this work presents the development of an FPGA-based T&E tool that allows for real-time pseudo-random signal generation for testing radio frequency receiver hardware (such as communication receivers, spectrum sensors, etc.). In particular, a framework is developed for an FPGA-based implementation of a test signal emulator that allows for user-defined randomization of test signal parameters such as center frequencies, bandwidths, start times, and durations, as well as receiver and channel effects such as additive white Gaussian noise (AWGN). To test the accuracy of the developed emulation framework, the randomization properties of the framework are analyzed to assure correct probability distributions and independence. Additionally, FPGA implementation decisions such as bit precision vs. accuracy of the generated signal and the impact on the FPGA’s hardware footprint are analyzed. Ultimately, it is shown that this framework is easily extensible to other signal types and channel models.