{"title":"带横向PIN检测器的2.5 Gbps CMOS全集成光接收器","authors":"Wei-Zen Chen, Shih-Hao Huang","doi":"10.1109/CICC.2007.4405736","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a monolithically integrated CMOS optical receiver, including a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. A novel PIN detector is proposed and adopted in this design without technology modification. The optical receiver is capable of delivering 420 mVpp to 50 Omega output load and operating up to 2.5 Gbps without an equalizer. Implemented in a generic 0.18 mum CMOS technology, the total power dissipation is 138 mW. The chip size is 0.53 mm2.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"48","resultStr":"{\"title\":\"A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector\",\"authors\":\"Wei-Zen Chen, Shih-Hao Huang\",\"doi\":\"10.1109/CICC.2007.4405736\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of a monolithically integrated CMOS optical receiver, including a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. A novel PIN detector is proposed and adopted in this design without technology modification. The optical receiver is capable of delivering 420 mVpp to 50 Omega output load and operating up to 2.5 Gbps without an equalizer. Implemented in a generic 0.18 mum CMOS technology, the total power dissipation is 138 mW. The chip size is 0.53 mm2.\",\"PeriodicalId\":130106,\"journal\":{\"name\":\"2007 IEEE Custom Integrated Circuits Conference\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"48\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2007.4405736\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2007.4405736","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 48
摘要
本文介绍了一种单片集成CMOS光接收器的设计,包括光检测器、跨阻放大器和限流放大器。提出了一种新的PIN检测器,并在不修改技术的情况下采用。光接收器能够在50 Omega输出负载下提供420 mVpp,在没有均衡器的情况下运行高达2.5 Gbps。采用通用的0.18 μ m CMOS技术,总功耗为138mw。芯片尺寸为0.53 mm2。
A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector
This paper presents the design of a monolithically integrated CMOS optical receiver, including a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. A novel PIN detector is proposed and adopted in this design without technology modification. The optical receiver is capable of delivering 420 mVpp to 50 Omega output load and operating up to 2.5 Gbps without an equalizer. Implemented in a generic 0.18 mum CMOS technology, the total power dissipation is 138 mW. The chip size is 0.53 mm2.