基于新型优化结构的新型高速双模预分频器设计

Zheng Sun, Yong Xu, Cheng Hu, G. Ma, Yuanliang Wu, Ying Huang
{"title":"基于新型优化结构的新型高速双模预分频器设计","authors":"Zheng Sun, Yong Xu, Cheng Hu, G. Ma, Yuanliang Wu, Ying Huang","doi":"10.1109/ASICON.2013.6811890","DOIUrl":null,"url":null,"abstract":"A kind of novel method is discussed to design the high speed prescaler in GHz frequency-hopping PLL frequency synthesizer. The structure of the dual-modulus prescaler (DMP) is optimized and a novel high speed D-latch integrated with multiple-input OR gate is used. The improved structure can make all separated logic gates be integrated with correlative D flip-flops completely. The circuit can work stably and accurately under all kinds of simulation condition such as different process corners. It is fabricated in 0.18μm mixed-signal CMOS technology. The measured results show that the high speed prscaler 's operating frequency range is 2.25~ 2.75GHz in 1.8V power supply, the current consumption is 5.4mA (including buffer) and higher speed and lower power dissipation are obtained.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of novel high speed dual-modulus prescaler based on new optimized structure\",\"authors\":\"Zheng Sun, Yong Xu, Cheng Hu, G. Ma, Yuanliang Wu, Ying Huang\",\"doi\":\"10.1109/ASICON.2013.6811890\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A kind of novel method is discussed to design the high speed prescaler in GHz frequency-hopping PLL frequency synthesizer. The structure of the dual-modulus prescaler (DMP) is optimized and a novel high speed D-latch integrated with multiple-input OR gate is used. The improved structure can make all separated logic gates be integrated with correlative D flip-flops completely. The circuit can work stably and accurately under all kinds of simulation condition such as different process corners. It is fabricated in 0.18μm mixed-signal CMOS technology. The measured results show that the high speed prscaler 's operating frequency range is 2.25~ 2.75GHz in 1.8V power supply, the current consumption is 5.4mA (including buffer) and higher speed and lower power dissipation are obtained.\",\"PeriodicalId\":150654,\"journal\":{\"name\":\"2013 IEEE 10th International Conference on ASIC\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE 10th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASICON.2013.6811890\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 10th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2013.6811890","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

讨论了在GHz跳频锁相环频率合成器中设计高速预分频器的一种新方法。对双模预分频器(DMP)的结构进行了优化,采用了一种集成多输入OR门的高速d锁存器。改进后的结构可以使所有分离的逻辑门与相关的D触发器完全集成。该电路在不同工艺转角等各种仿真条件下均能稳定、准确地工作。采用0.18μm混合信号CMOS工艺制造。测量结果表明,在1.8V电源下,高速滤波器的工作频率范围为2.25~ 2.75GHz,电流消耗为5.4mA(含缓冲器),获得了更高的速度和更低的功耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of novel high speed dual-modulus prescaler based on new optimized structure
A kind of novel method is discussed to design the high speed prescaler in GHz frequency-hopping PLL frequency synthesizer. The structure of the dual-modulus prescaler (DMP) is optimized and a novel high speed D-latch integrated with multiple-input OR gate is used. The improved structure can make all separated logic gates be integrated with correlative D flip-flops completely. The circuit can work stably and accurately under all kinds of simulation condition such as different process corners. It is fabricated in 0.18μm mixed-signal CMOS technology. The measured results show that the high speed prscaler 's operating frequency range is 2.25~ 2.75GHz in 1.8V power supply, the current consumption is 5.4mA (including buffer) and higher speed and lower power dissipation are obtained.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信