卷积神经网络的Hartley随机计算

S. H. Mozafari, J. Clark, W. Gross, B. Meyer
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引用次数: 1

摘要

卷积神经网络(cnn)的能量消耗和延迟是限制其应用于嵌入式设备的两个重要因素。基于傅里叶的频域(FD)卷积是一种有前途的低成本替代cnn在空间域(SD)的传统实现。FD卷积用逐点乘法执行其操作。然而,在cnn中,基于傅里叶的fd -卷积的开销超过了小滤波器尺寸的计算节省。在这项工作中,我们建议在FD中使用Hartley变换(HT)而不是傅里叶变换来实现卷积层。我们证明了HT可以减少卷积延迟和能量消耗,即使是小滤波器。对于参数的HT,我们用逐点乘法代替卷积。HT让我们在所有卷积层中压缩输入特征映射,然后再与过滤器进行卷积。为了优化我们方法的硬件实现,我们利用随机计算(SC)在FD中执行逐点乘法。在这方面,我们重新形式化了HT以更好地匹配SC。我们表明,与传统的基于傅立叶的卷积相比,当我们在CIFAR-10上实现AlexNet时,基于Hartley SC的卷积可以在Virtex 7 FPGA上实现1.33倍的加速和1.23倍的节能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Hartley Stochastic Computing For Convolutional Neural Networks
Energy consumption and the latency of convolutional neural networks (CNNs) are two important factors that limit their applications specifically for embedded devices. Fourier-based frequency domain (FD) convolution is a promising low-cost alter-native to conventional implementations in the spatial domain (SD) for CNNs. FD convolution performs its operation with point-wise multiplications. However, in CNNs, the overhead for the Fourier-based FD-convolution surpasses its computational saving for small filter sizes. In this work, we propose to implement convolutional layers in the FD using the Hartley transformation (HT) instead of the Fourier transformation. We show that the HT can reduce the convolution delay and energy consumption even for small filters. With the HT of parameters, we replace convolution with point-wise multiplications. HT lets us compress input feature maps, in all convolutional layer, before convolving them with filters. To optimize the hardware implementation of our method, we utilize stochastic computing (SC) to perform the point-wise multiplications in the FD. In this regard, we re-formalize the HT to better match with SC. We show that, compared to conventional Fourier-based convolution, Hartley SC-based convolution can achieve 1.33x speedup, and 1.23x energy saving on a Virtex 7 FPGA when we implement AlexNet over CIFAR-10.
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