{"title":"芯片上ESD保护设计采用多晶硅二极管的CMOS技术用于智能卡应用","authors":"Tai-Ho Wang, M. Ker","doi":"10.1109/EOSESD.2000.890086","DOIUrl":null,"url":null,"abstract":"A novel on-chip ESD protection design using polysilicon diodes for a smart card application is reported in this paper. By adding an efficient V/sub DD/-to-V/sub SS/ clamp circuit, the HBM ESD level of the smart card IC with polysilicon diodes as the ESD protection devices have been successfully improved from the original /spl sim/300 V to become /spl ges/3 kV. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimization of the polysilicon diodes for both smart card application and on-chip ESD protection design.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application\",\"authors\":\"Tai-Ho Wang, M. Ker\",\"doi\":\"10.1109/EOSESD.2000.890086\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel on-chip ESD protection design using polysilicon diodes for a smart card application is reported in this paper. By adding an efficient V/sub DD/-to-V/sub SS/ clamp circuit, the HBM ESD level of the smart card IC with polysilicon diodes as the ESD protection devices have been successfully improved from the original /spl sim/300 V to become /spl ges/3 kV. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimization of the polysilicon diodes for both smart card application and on-chip ESD protection design.\",\"PeriodicalId\":332394,\"journal\":{\"name\":\"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-09-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EOSESD.2000.890086\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EOSESD.2000.890086","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application
A novel on-chip ESD protection design using polysilicon diodes for a smart card application is reported in this paper. By adding an efficient V/sub DD/-to-V/sub SS/ clamp circuit, the HBM ESD level of the smart card IC with polysilicon diodes as the ESD protection devices have been successfully improved from the original /spl sim/300 V to become /spl ges/3 kV. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimization of the polysilicon diodes for both smart card application and on-chip ESD protection design.