{"title":"芯片组和系统的性能分析","authors":"D. Lutz, B. Kahne","doi":"10.1109/PCCC.1999.749470","DOIUrl":null,"url":null,"abstract":"Plasma is a new tool for modeling the timing of chipsets and other system components. Modeling chipsets is in some ways more difficult than modeling processors: the interfaces are more complex and more numerous, the internal queues and buffers are larger, and the traces are much more complicated. We have used Plasma to create a timing model for a modern chipset. The resulting model is fast, flexible, and useful for both design and verification.","PeriodicalId":211210,"journal":{"name":"1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Performance analysis for chipsets and systems\",\"authors\":\"D. Lutz, B. Kahne\",\"doi\":\"10.1109/PCCC.1999.749470\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Plasma is a new tool for modeling the timing of chipsets and other system components. Modeling chipsets is in some ways more difficult than modeling processors: the interfaces are more complex and more numerous, the internal queues and buffers are larger, and the traces are much more complicated. We have used Plasma to create a timing model for a modern chipset. The resulting model is fast, flexible, and useful for both design and verification.\",\"PeriodicalId\":211210,\"journal\":{\"name\":\"1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305)\",\"volume\":\"84 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-02-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PCCC.1999.749470\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PCCC.1999.749470","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Plasma is a new tool for modeling the timing of chipsets and other system components. Modeling chipsets is in some ways more difficult than modeling processors: the interfaces are more complex and more numerous, the internal queues and buffers are larger, and the traces are much more complicated. We have used Plasma to create a timing model for a modern chipset. The resulting model is fast, flexible, and useful for both design and verification.