Analysis of full adder using adiabatic charge recovery logic

Advancement in technology has lead to an increased demand for low power devices. Hence power has become a critical design parameter in low power and high performance applications. In most of the digital circuits, digital signal processing and communication systems, multipliers play a major role where adders constitute the basic blocks. Adders with huge power consumption affect the overall efficiency of the system. Adiabatic logic is a promising design paradigm for low power circuits since the energy which is to be dissipated is recycled back. Adders based on conventional CMOS circuits consume much power thereby affecting the overall efficiency of the circuit. This paper presents a comparative study of full adder using different adiabatic logic styles. Power analysis is carried out at 45nm for different frequencies and results show that at low frequencies Efficient Charge Recovery Logic (ECRL) consumes 69% less power than CMOS whereas at higher frequencies the power consumption of Secured-Quasi Adiabatic Logic (SQAL) is 71.8% lesser than CMOS.