{"title":"基于C-2C梯形D/A转换器的双金属CMOS工艺","authors":"S.P. Singh, J. Hanson, J. Vlach","doi":"10.1109/PACRIM.1989.48310","DOIUrl":null,"url":null,"abstract":"Three 8-bit C-2C ladder based D/A converter circuits are presented that utilize interlayer capacitors available in a two-metal CMOS process and need no process modification. The capacitances, being of a similar order, are used to form individual capacitors in the C-2C ladder. This leads to a lower unit capacitor number requirement and a saving of silicon area.<<ETX>>","PeriodicalId":256287,"journal":{"name":"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"C-2C ladder based D/A converters for two metal CMOS process\",\"authors\":\"S.P. Singh, J. Hanson, J. Vlach\",\"doi\":\"10.1109/PACRIM.1989.48310\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Three 8-bit C-2C ladder based D/A converter circuits are presented that utilize interlayer capacitors available in a two-metal CMOS process and need no process modification. The capacitances, being of a similar order, are used to form individual capacitors in the C-2C ladder. This leads to a lower unit capacitor number requirement and a saving of silicon area.<<ETX>>\",\"PeriodicalId\":256287,\"journal\":{\"name\":\"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PACRIM.1989.48310\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PACRIM.1989.48310","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
C-2C ladder based D/A converters for two metal CMOS process
Three 8-bit C-2C ladder based D/A converter circuits are presented that utilize interlayer capacitors available in a two-metal CMOS process and need no process modification. The capacitances, being of a similar order, are used to form individual capacitors in the C-2C ladder. This leads to a lower unit capacitor number requirement and a saving of silicon area.<>