通过降低CMP压力提高多孔低k/Cu集成的电过收率

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) Pub Date : 2004-06-07 DOI:10.1109/IITC.2004.1345716

S. Tokitoh, S. Kondo, B. Yoon, A. Namiki, K. Inukai, K. Misawa, S. Sone, H.J. Shin, Y. Matsubara, N. Ohashi, N. Kobayashi

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引用次数: 2

摘要

研究了CMP压力对由多孔低钾膜组成的双、单衬底互连的通孔电阻率的影响。采用不同机械强度(杨氏模量和硬度)的多孔低钾薄膜。发现过孔电阻产率强烈依赖于过孔层的CMP压力和过孔低k膜的机械强度。综合考虑CMP工艺的力学和化学方面的结果分析表明，使用低压CMP (1.5 psi)可以使由具有高机械强度(E=9.8GPa, H=1.2GPa)的多孔低k (k=2.3)膜组成的Cu互连具有优异的电性能。

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Enhancement in electrical via-yield of porous low-k/Cu integration by reducing CMP pressure

The effects of CMP pressure on the via resistance yield of dual- and single-damascene interconnects consisting of porous low-k films have been investigated. Porous low-k films with different mechanical strengths (Young's modulus and hardness) were used. The via resistance yield was found to strongly depend on both the CMP pressure of the via-layer and mechanical strength of the via low-k film. Analysis of the results considering the mechanical and chemical aspects of the CMP process showed that using low-pressure CMP (1.5 psi) resulted in excellent electrical properties for Cu interconnects composed of the porous low-k (k=2.3) film with high mechanical strength (E=9.8GPa, H=1.2GPa).

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Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)

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