Markus Stadelmayer, Tim Schumacher, Thomas Faseth, H. Pretl
{"title":"一种基于1.2 v 180 nm CMOS低功耗多波段环形振荡器的频率合成器,用于边合发射机","authors":"Markus Stadelmayer, Tim Schumacher, Thomas Faseth, H. Pretl","doi":"10.1109/newcas49341.2020.9159846","DOIUrl":null,"url":null,"abstract":"A wide-frequency-range low-power synthesizer based on an eight-stage differential ring oscillator (RO) regulated by a phase locked loop (PLL) is introduced. It is specially designed to be used in edge-combining transmitters and fabricated in a 180nm 1P6M CMOS process. It provides 16 symmetrical phase-shifted outputs for up to 8-times frequency-multiplication using an external edge-combiner. The oscillator is implemented as current-starved RO. It includes a biasing network with threshold regulation for close to 50% duty cycle and equal time delay in all RO stages. The lower corner-frequency is 5 bit adjustable (50MHz to 300 MHz) and the oscillator offers an additional 5 bit trimmable tuning range (20.3MHz to 97.2 MHz). The structure is optimized to operate at 216MHz and shows a phase noise of −96 dBc/Hz at 1MHz offset as well as −76 dBc/Hz in-band phase noise (with locked PLL below 100 kHz offset). With its low power demand of 1.3mW, the frequency synthesizer is suited to be used in low-power transmitters.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 1.2-V 180-nm CMOS Low-Power Multi-Band Ring Oscillator based Frequency Synthesizer for Edge-Combining Transmitters\",\"authors\":\"Markus Stadelmayer, Tim Schumacher, Thomas Faseth, H. Pretl\",\"doi\":\"10.1109/newcas49341.2020.9159846\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A wide-frequency-range low-power synthesizer based on an eight-stage differential ring oscillator (RO) regulated by a phase locked loop (PLL) is introduced. It is specially designed to be used in edge-combining transmitters and fabricated in a 180nm 1P6M CMOS process. It provides 16 symmetrical phase-shifted outputs for up to 8-times frequency-multiplication using an external edge-combiner. The oscillator is implemented as current-starved RO. It includes a biasing network with threshold regulation for close to 50% duty cycle and equal time delay in all RO stages. The lower corner-frequency is 5 bit adjustable (50MHz to 300 MHz) and the oscillator offers an additional 5 bit trimmable tuning range (20.3MHz to 97.2 MHz). The structure is optimized to operate at 216MHz and shows a phase noise of −96 dBc/Hz at 1MHz offset as well as −76 dBc/Hz in-band phase noise (with locked PLL below 100 kHz offset). With its low power demand of 1.3mW, the frequency synthesizer is suited to be used in low-power transmitters.\",\"PeriodicalId\":135163,\"journal\":{\"name\":\"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/newcas49341.2020.9159846\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/newcas49341.2020.9159846","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.2-V 180-nm CMOS Low-Power Multi-Band Ring Oscillator based Frequency Synthesizer for Edge-Combining Transmitters
A wide-frequency-range low-power synthesizer based on an eight-stage differential ring oscillator (RO) regulated by a phase locked loop (PLL) is introduced. It is specially designed to be used in edge-combining transmitters and fabricated in a 180nm 1P6M CMOS process. It provides 16 symmetrical phase-shifted outputs for up to 8-times frequency-multiplication using an external edge-combiner. The oscillator is implemented as current-starved RO. It includes a biasing network with threshold regulation for close to 50% duty cycle and equal time delay in all RO stages. The lower corner-frequency is 5 bit adjustable (50MHz to 300 MHz) and the oscillator offers an additional 5 bit trimmable tuning range (20.3MHz to 97.2 MHz). The structure is optimized to operate at 216MHz and shows a phase noise of −96 dBc/Hz at 1MHz offset as well as −76 dBc/Hz in-band phase noise (with locked PLL below 100 kHz offset). With its low power demand of 1.3mW, the frequency synthesizer is suited to be used in low-power transmitters.