基于排队理论的NoC性能评估在实际科学应用中的应用

Carlos A. Piedrahita-Velásquez, Gustavo Patiño, Juan Pablo Urrea Duque
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引用次数: 0

摘要

片上网络(NoC)的性能指标评估是多处理器片上系统(MPSoC)设计中越来越重要的一个方面。随着系统组件和功能的增加,片上网络的正确设计在满足系统的性能要求方面起着核心作用,因为它负责MPSoC内部数据的有效移动。本文提出了一种基于排队理论的NoC模拟器软件,用于估计NoC的时延和吞吐量。该工具的贡献在于它能够根据科学应用的真实数据流量生成随机流量模式,而不仅仅是文献中报道的合成流量。这使得在实际工作条件下研究NoC性能成为可能,从而更好地了解NoC行为,并改善系统开发早期阶段的设计空间探索。nosimulator使用两个最先进的周期精确模拟器(BookSim和Garnet)进行验证。基于排队理论的NoC模拟器没有将NoC的硬件方面建模为周期精确的模拟器,因此在设计空间探索时可以避免复杂系统的长时间仿真。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
NoC Performance Estimation Based on Queueing Theory for Real Scientific Applications
The estimation of performance metrics of a Network-on-Chip (NoC) is an increasingly important aspect of Multiprocessor System-on-Chip (MPSoC) design. As systems grow in number of components and features, the correct design of the Network-on-Chip has a central role in meeting the performance requirements of the system, because it is responsible for the efficient movement of data inside the MPSoC. In this paper a software tool called NoCSimulator which is based in queueing theory for the estimation of latency and throughput of a NoC is proposed. The contribution of this tool is its ability to generate stochastic traffic patterns based on real data traffic of scientific applications, not only synthetic traffic as similar tools reported in literature. This makes it possible to study NoC performance under real working conditions, which gives better insights about NoC behavior, and improves the design space exploration at early stages of system development. NoCSimulator was validated using two state-of-the-art cycle-accurate simulators (BookSim and Garnet). NoCSimulator, based in queueing theory, does not model hardware aspects of the NoC as a cycle-accurate simulator, so, long simulation times of complex systems can be avoided during design space exploration.
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