Study on Leakage Current Reduction Technique in VLSI Design

In the present scenario, designing a circuit with low power has become very important and challenging task, low power devices are the need of present electronics industries. In VLSI circuit design, power dissipation and leakage present are the critical design structures as they show anvital role in act of the battery. Power management of chip is the major challenge. Leakage power is a crucial parameter as the technology is shrinking (180 nanometer, 90 nanometer, 45 nanometer).The leakage current is increasing very fast so numerous technique has been proposed for leakage reduction in CMOS digital integrated circuit. This review paper demonstrates the various reduction showcase for CMOS integrated circuited.