{"title":"一种新的容噪动态逻辑电路设计","authors":"F. Frustaci, P. Corsonello, G. Cocorullo","doi":"10.1109/RME.2007.4401855","DOIUrl":null,"url":null,"abstract":"This work proposes a new noise-tolerant dynamic circuit design. It has been extensively compared to previously published schemes. The new design can achieve a level of noise robustness that is unreachable by the previous proposals. Furthermore, it has minimal delay and energy penalties. Under the same energy-delay product, the proposed design shows a noise-robustness that is increased by up to 116%, in comparison with the existing schemes.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"27","resultStr":"{\"title\":\"A new noise-tolerant dynamic logic circuit design\",\"authors\":\"F. Frustaci, P. Corsonello, G. Cocorullo\",\"doi\":\"10.1109/RME.2007.4401855\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work proposes a new noise-tolerant dynamic circuit design. It has been extensively compared to previously published schemes. The new design can achieve a level of noise robustness that is unreachable by the previous proposals. Furthermore, it has minimal delay and energy penalties. Under the same energy-delay product, the proposed design shows a noise-robustness that is increased by up to 116%, in comparison with the existing schemes.\",\"PeriodicalId\":118230,\"journal\":{\"name\":\"2007 Ph.D Research in Microelectronics and Electronics Conference\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-07-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"27\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 Ph.D Research in Microelectronics and Electronics Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RME.2007.4401855\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 Ph.D Research in Microelectronics and Electronics Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RME.2007.4401855","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This work proposes a new noise-tolerant dynamic circuit design. It has been extensively compared to previously published schemes. The new design can achieve a level of noise robustness that is unreachable by the previous proposals. Furthermore, it has minimal delay and energy penalties. Under the same energy-delay product, the proposed design shows a noise-robustness that is increased by up to 116%, in comparison with the existing schemes.
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